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| author |   Fathi Boudra <fathi.boudra@linaro.org> | 2015-04-10 10:16:19 +0300 |
|---|---|---|
| committer |   Wei Xu <xuwei5@hisilicon.com> | 2015-05-08 01:57:51 +0100 |
| commit | 9fac45c16c33f9f822ed7f9b9660890f68f16d8b (patch) | |
| tree | 0b11f2c11bceded8dd1d35da08e077564fe24a16 | |
| parent | mtd: hisilicon: add device tree node for NAND controller (diff) | |
| download | wireguard-linux-9fac45c16c33f9f822ed7f9b9660890f68f16d8b.tar.xz wireguard-linux-9fac45c16c33f9f822ed7f9b9660890f68f16d8b.zip | |
ARM: dts: add HiSilicon hip04 ethernet controller resource
add the device tree binding for the HiSilicon hip04 ethernet controller
based on Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| -rw-r--r-- | arch/arm/boot/dts/hip04.dtsi | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 027d06c06322..6434b7f91329 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -352,6 +352,56 @@ #address-cells = <1>; #size-cells = <1>; }; + + mdio { + compatible = "hisilicon,hip04-mdio"; + reg = <0x28f1000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <18 0x14 0 0x8001>; + }; + }; + + ppe: ppe@28c0000 { + compatible = "hisilicon,hip04-ppe", "syscon"; + reg = <0x28c0000 0x10000>; + }; + + fe: ethernet@28b0000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x28b0000 0x10000>; + interrupts = <0 413 4>; + phy-mode = "mii"; + port-handle = <&ppe 31 0>; + }; + + ge0: ethernet@2800000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2800000 0x10000>; + interrupts = <0 402 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 0 1>; + phy-handle = <&phy0>; + }; + + ge8: ethernet@2880000 { + compatible = "hisilicon,hip04-mac"; + reg = <0x2880000 0x10000>; + interrupts = <0 410 4>; + phy-mode = "sgmii"; + port-handle = <&ppe 8 2>; + phy-handle = <&phy1>; + }; }; etb@0,e3c42000 { |