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| author |   Thierry Reding <treding@nvidia.com> | 2020-05-13 12:59:28 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-13 12:59:28 +0200 |
| commit | 9fb276934a5d8fca4adadad18d2679e596f0ca0a (patch) | |
| tree | 06bb2cd80c908f38633cfec262d52bf999adbfff | |
| parent | Linux 5.7-rc1 (diff) | |
| parent | dt-bindings: clock: tegra: Add clock ID for CSI TPG clock (diff) | |
| download | wireguard-linux-9fb276934a5d8fca4adadad18d2679e596f0ca0a.tar.xz wireguard-linux-9fb276934a5d8fca4adadad18d2679e596f0ca0a.zip | |
Merge branch 'for-5.8/dt-bindings' into for-5.8/arm64/dt
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b9a66d..99c598694923 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -358,7 +358,7 @@ #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 /* 325 */ #define TEGRA210_CLK_OSC 326 -/* 327 */ +#define TEGRA210_CLK_CSI_TPG 327 /* 328 */ /* 329 */ /* 330 */ |