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| author |   Aurabindo Pillai <aurabindo.pillai@amd.com> | 2023-04-06 16:16:33 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-04-21 08:50:20 -0400 |
| commit | a1f1fecd04f0b9ef600898c7f9b2094504127fd7 (patch) | |
| tree | b622a8aae264fffb6bffbd88e60a45fe859cc9f5 | |
| parent | drm/amd/display: add support for low bpc (diff) | |
| download | wireguard-linux-a1f1fecd04f0b9ef600898c7f9b2094504127fd7.tar.xz wireguard-linux-a1f1fecd04f0b9ef600898c7f9b2094504127fd7.zip | |
drm/amd/display: Set DRAM clock if retraining is required
Set DRAM clock change state if retraining is required.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index cad2bc3aea67..d39e77d95fc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -4338,7 +4338,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; } if (v->USRRetrainingRequiredFinal) - v->Watermark.WritebackUrgentWatermark = v->Watermark.WritebackUrgentWatermark + v->Watermark.WritebackDRAMClockChangeWatermark = v->Watermark.WritebackDRAMClockChangeWatermark + mmSOCParameters.USRRetrainingLatency; if (TotalActiveWriteback <= 1) { |