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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-12-10 19:09:50 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-12-13 11:21:52 +0100 |
| commit | a94253232b0454ae3f45e2a941bbc0a1d5bdb955 (patch) | |
| tree | c7b18760abce7056b2ea299418e17d46d1182105 | |
| parent | arm64: dts: renesas: r9a08g045: Add SSI nodes (diff) | |
| download | wireguard-linux-a94253232b0454ae3f45e2a941bbc0a1d5bdb955.tar.xz wireguard-linux-a94253232b0454ae3f45e2a941bbc0a1d5bdb955.zip | |
arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node
Add versa3 clock generator node. It provides the clocks for the Ethernet
PHY, PCIe, audio devices.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 4ee91ea05261..5117de3c8c4b 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -87,6 +87,12 @@ gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &adc { @@ -151,6 +157,30 @@ &i2c1 { status = "okay"; + + versa3: clock-generator@68 { + compatible = "renesas,5l35023"; + reg = <0x68>; + clocks = <&x3_clk>; + #clock-cells = <1>; + assigned-clocks = <&versa3 0>, + <&versa3 1>, + <&versa3 2>, + <&versa3 3>, + <&versa3 4>, + <&versa3 5>; + assigned-clock-rates = <24000000>, + <12288000>, + <11289600>, + <25000000>, + <100000000>, + <100000000>; + renesas,settings = [ + 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27 + 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86 + a0 80 30 30 9c + ]; + }; }; #if SW_CONFIG2 == SW_ON |