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| author |   Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2023-04-02 12:50:51 +0300 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-04-05 19:30:20 +0200 |
| commit | b46a22dea7530cf530a45c6b84c03300083b813d (patch) | |
| tree | 9ec1ce0d1592e61f42886a790e2c34b48c4bcc94 | |
| parent | arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s (diff) | |
| download | wireguard-linux-b46a22dea7530cf530a45c6b84c03300083b813d.tar.xz wireguard-linux-b46a22dea7530cf530a45c6b84c03300083b813d.zip | |
arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s
The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.
Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 37d03330a37e..5e27905b9d6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -416,7 +416,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, |