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authorTaimur Hassan <Syed.Hassan@amd.com>2025-03-09 04:57:46 -0400
committerAlex Deucher <alexander.deucher@amd.com>2025-03-18 14:03:47 -0400
commitbed6bc66e84c47079a4e70f22cf1d8b60a998b8b (patch)
treed9d87f3539dd0bd586cb1c2c7c9b68a49c3e9dee
parentdrm/amd/display: Use DPM table clk setting for dml2 soc dscclk (diff)
downloadwireguard-linux-bed6bc66e84c47079a4e70f22cf1d8b60a998b8b.tar.xz
wireguard-linux-bed6bc66e84c47079a4e70f22cf1d8b60a998b8b.zip
drm/amd/display: 3.2.325
This version brings along following fixes: - Use DPM table clk setting for dml2 soc dscclk - Update static soc table - Fix incorrect fw_state address in dmub_srv - Use HW lock mgr for PSR1 when only one eDP - Revert "Support for reg inbox0 for host->DMUB CMDs" - Change notification of link BW allocation - Fix message for support_edp0_on_dp1 - Guard against setting dispclk low for dcn31x - Prevent VStartup Overflow - Check pipe->stream before passing it to a function Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7932d8f99d22..7c2ee0526926 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -53,7 +53,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
-#define DC_VER "3.2.324"
+#define DC_VER "3.2.325"
/**
* MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC