diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-01-16 22:16:30 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-01-21 17:12:44 +0200 |
| commit | c5303240e01919ea9cd3a2e198c3a25686a99552 (patch) | |
| tree | dc8a3f7a86b3df265d8d1b0265c52d96656aff2e | |
| parent | drm/xe/dp: Fix non-display builds with DP tunnelling incorrectly enabled (diff) | |
| download | wireguard-linux-c5303240e01919ea9cd3a2e198c3a25686a99552.tar.xz wireguard-linux-c5303240e01919ea9cd3a2e198c3a25686a99552.zip | |
drm/i915: Keep TRANS_VBLANK.vblank_start==0 on ADL+ even when doing LRR updates
intel_set_transcoder_timings() will set TRANS_VBLANK.vblank_start to 0
for clarity on ADL+ (non-DSI) because the hardware no longer uses that
value. Do the same in intel_set_transcoder_timings_lrr() to make sure
the registers stay consistent even when doing LRR timing updates.
Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250116201637.22486-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e63619da2e62..34b8a54f95a3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2923,6 +2923,14 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc crtc_vblank_start = adjusted_mode->crtc_vblank_start; crtc_vblank_end = adjusted_mode->crtc_vblank_end; + if (DISPLAY_VER(dev_priv) >= 13) { + /* + * VBLANK_START not used by hw, just clear it + * to make it stand out in register dumps. + */ + crtc_vblank_start = 1; + } + drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE); /* |