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| author |   Chuan Liu <chuan.liu@amlogic.com> | 2024-09-09 18:08:56 +0800 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2024-09-30 11:27:36 +0200 |
| commit | c939154e8417d5e04865ff0e45ec8e78592b262d (patch) | |
| tree | 5570bcbb53ce1cc7c26d6a605b894c70e7fd0c53 | |
| parent | clk: meson: s4: pll: hifi_pll support fractional multiplier (diff) | |
| download | wireguard-linux-c939154e8417d5e04865ff0e45ec8e78592b262d.tar.xz wireguard-linux-c939154e8417d5e04865ff0e45ec8e78592b262d.zip | |
clk: meson: Support PLL with fixed fractional denominators
Some PLLS with fractional multipliers have fractional denominators with
fixed values, instead of the previous "(1 << pll-> frc.width)".
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-1-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| -rw-r--r-- | drivers/clk/meson/clk-pll.c | 8 | ||||
| -rw-r--r-- | drivers/clk/meson/clk-pll.h | 1 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index bc570a2ff3a3..89f0f04a16ab 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -57,12 +57,13 @@ static unsigned long __pll_params_to_rate(unsigned long parent_rate, struct meson_clk_pll_data *pll) { u64 rate = (u64)parent_rate * m; + unsigned int frac_max = pll->frac_max ? pll->frac_max : + (1 << pll->frac.width); if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { u64 frac_rate = (u64)parent_rate * frac; - rate += DIV_ROUND_UP_ULL(frac_rate, - (1 << pll->frac.width)); + rate += DIV_ROUND_UP_ULL(frac_rate, frac_max); } return DIV_ROUND_UP_ULL(rate, n); @@ -100,7 +101,8 @@ static unsigned int __pll_params_with_frac(unsigned long rate, unsigned int n, struct meson_clk_pll_data *pll) { - unsigned int frac_max = (1 << pll->frac.width); + unsigned int frac_max = pll->frac_max ? pll->frac_max : + (1 << pll->frac.width); u64 val = (u64)rate * n; /* Bail out if we are already over the requested rate */ diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 7b6b87274073..949157fb7bf5 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -43,6 +43,7 @@ struct meson_clk_pll_data { unsigned int init_count; const struct pll_params_table *table; const struct pll_mult_range *range; + unsigned int frac_max; u8 flags; }; |