diff options
| author | 2024-11-05 16:09:16 +0530 | |
|---|---|---|
| committer | 2024-11-19 13:26:52 +0530 | |
| commit | ca596b781a8081a14077f1e902b4ce43c1fd8fb2 (patch) | |
| tree | c2e14fc172433c6b2475912b0b0865d28c941172 | |
| parent | drm/i915/dp_mst: Fix connector initialization in intel_dp_add_mst_connector() (diff) | |
| download | wireguard-linux-ca596b781a8081a14077f1e902b4ce43c1fd8fb2.tar.xz wireguard-linux-ca596b781a8081a14077f1e902b4ce43c1fd8fb2.zip | |
drm/i915/psr: Disable psr1 if setup_time > vblank
Issue is seen when PSR enabled with setup frames and when try to disable
PSR at SRDONACK State (0x1). PSR FSM is stuck at SRDONACK(0x1) for more
than 5 seconds. Issue not seen with Setup frames disabled. Currently
disable psr1 if setuptime > vblank to workaround the above issue.
HSD: 16024594674
WA: 18037818876
v1: Initial version
v2: Add debug log and some cosmetic changes. [Jouni, Jani, Nemesa]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241105103916.1857731-1-animesh.manna@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3c498b3ed175..15b70a1127d4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1637,6 +1637,15 @@ _panel_replay_compute_config(struct intel_dp *intel_dp, return true; } +static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(intel_dp); + + return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && + !crtc_state->has_sel_update); +} + void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -1689,6 +1698,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); + + /* Wa_18037818876 */ + if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { + crtc_state->has_psr = false; + drm_dbg_kms(display->drm, + "PSR disabled to workaround PSR FSM hang issue\n"); + } } void intel_psr_get_config(struct intel_encoder *encoder, |
