diff options
| author |   Florian Fainelli <f.fainelli@gmail.com> | 2020-02-19 12:00:48 -0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-02-19 16:36:48 -0800 |
| commit | cb64da3a5b60b7e9312ade2d6892a1fe657d23b1 (patch) | |
| tree | 6c96d362aa057ab86561442473c1f051f6e8110b | |
| parent | net: phy: broadcom: Allow BCM54810 to use bcm54xx_adjust_rxrefclk() (diff) | |
| download | wireguard-linux-cb64da3a5b60b7e9312ade2d6892a1fe657d23b1.tar.xz wireguard-linux-cb64da3a5b60b7e9312ade2d6892a1fe657d23b1.zip | |
net: phy: broadcom: Have bcm54xx_adjust_rxrefclk() check for flags
bcm54xx_adjust_rxrefclk() already checks for PHY_BRCM_AUTO_PWRDWN_ENABLE
and PHY_BRCM_DIS_TXCRXC_NOENRGY in order to set the appropriate bit. The
situation is a bit more complicated with the flag
PHY_BRCM_RX_REFCLK_UNUSED but essentially amounts to the same situation.
The default setting for the 125MHz clock is to be on for all PHYs and
we still treat BCM50610 and BCM50610M specifically with the polarity of
the bit reversed.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/broadcom.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 4ad2128cc454..b4eae84a9195 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -273,10 +273,7 @@ static int bcm54xx_config_init(struct phy_device *phydev) (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); - if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) || - (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) || - (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) - bcm54xx_adjust_rxrefclk(phydev); + bcm54xx_adjust_rxrefclk(phydev); if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) { err = bcm54210e_config_init(phydev); |