diff options
| author |   Duncan Ma <duncan.ma@amd.com> | 2022-08-15 17:37:32 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-08-29 17:45:27 -0400 |
| commit | cfa1e7f8a75927e55cce1300c8fbda2e1d1e0abe (patch) | |
| tree | 37b848bac1d54d111f2d38ac2cf29c3f939f6fd2 | |
| parent | drm/amd/display: Refine aux transaction before retrieve caps (diff) | |
| download | wireguard-linux-cfa1e7f8a75927e55cce1300c8fbda2e1d1e0abe.tar.xz wireguard-linux-cfa1e7f8a75927e55cce1300c8fbda2e1d1e0abe.zip | |
drm/amd/display: Fix OTG H timing reset for dcn314
[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.
[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c index 0c7980266b85..38aa28ec6b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c @@ -98,7 +98,8 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mpcc_hactive); - REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); + REG_UPDATE(OTG_H_TIMING_CNTL, + OTG_H_TIMING_DIV_MODE, opp_cnt - 1); optc1->opp_count = opp_cnt; } |