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| author |   Alex Bee <knaerzche@gmail.com> | 2024-05-06 17:51:03 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2024-06-23 22:05:05 +0200 |
| commit | d244d6cc718a048672bfb148a6bc9c593a0e1207 (patch) | |
| tree | 04603398d436da33592b5dcb60feb6cac52440d1 | |
| parent | ARM: dts: rockchip: Add i2s nodes for RK3128 (diff) | |
| download | wireguard-linux-d244d6cc718a048672bfb148a6bc9c593a0e1207.tar.xz wireguard-linux-d244d6cc718a048672bfb148a6bc9c593a0e1207.zip | |
ARM: dts: rockchip: Add spdif node for RK3128
The SoC has a S/PDIF TX controller which is fully compatible with older
generation Rockchip SoCs.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240506155103.206592-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm/boot/dts/rockchip/rk3128.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 2c41a123c96a..4ced1f1fabea 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -411,6 +411,20 @@ status = "disabled"; }; + spdif: spdif@10204000 { + compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; + reg = <0x10204000 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; |