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| author |   Aapo Vienamo <avienamo@nvidia.com> | 2018-08-10 21:14:05 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2018-08-27 12:27:37 +0200 |
| commit | d5d6b468a0043579c3576ddbd4191c13837af672 (patch) | |
| tree | 09fee9c3e019e60ae202647d97e26ee0d1ccf321 | |
| parent | arm64: dts: tegra186: Add SDMMC4 DQS trim value (diff) | |
| download | wireguard-linux-d5d6b468a0043579c3576ddbd4191c13837af672.tar.xz wireguard-linux-d5d6b468a0043579c3576ddbd4191c13837af672.zip | |
arm64: dts: tegra210: Enable HS400
Enable HS400 signaling on Tegra210 SDMMC4 controller.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f8e5f0908ade..8fe47d6445a5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1116,6 +1116,7 @@ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; nvidia,dqs-trim = <40>; + mmc-hs400-1_8v; status = "disabled"; }; |