diff options
| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 16:46:31 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-04-21 12:31:41 -0500 |
| commit | df307c906c48d1c8c6ffb9022907bfb6cb041da6 (patch) | |
| tree | 46706d5459173f2c71e65c5d131d8eb45a61e238 | |
| parent | arm64: dts: qcom: msm8998: Add PCIe bridge node (diff) | |
| download | wireguard-linux-df307c906c48d1c8c6ffb9022907bfb6cb041da6.tar.xz wireguard-linux-df307c906c48d1c8c6ffb9022907bfb6cb041da6.zip | |
arm64: dts: qcom: sc7280: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-11-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bd9b1898d7a7..cea294a4ecfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2273,6 +2273,16 @@ <0x100 &apps_smmu 0x1c81 0x1>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { |