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| author |   Sunyeal Hong <sunyeal.hong@samsung.com> | 2024-10-09 13:21:10 +0900 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-10-10 10:52:36 +0200 |
| commit | ef1c2a54cbc7d9446659115c3a61e03f97ba4a57 (patch) | |
| tree | ec288662cb97cabf9734cf3c7512969155d8c93a | |
| parent | Merge branch 'for-v6.13/clk-dt-bindings' into next/dt64 (diff) | |
| download | wireguard-linux-ef1c2a54cbc7d9446659115c3a61e03f97ba4a57.tar.xz wireguard-linux-ef1c2a54cbc7d9446659115c3a61e03f97ba4a57.zip | |
arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes
Add cmu_peric1 for USI, I2C and I3C clocks respectively.
Add cmu_misc for MISC, GIC and OTP clocks respectively.
Add cmu_hsi0 for PCIE clocks respectively.
Add cmu_hsi1 for USB and MMC clocks respectively.
Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
Link: https://lore.kernel.org/r/20241009042110.2379903-4-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 91882b37fdb3..c759134c909e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -172,6 +172,17 @@ reg = <0x10000000 0x24>; }; + cmu_misc: clock-controller@10020000 { + compatible = "samsung,exynosautov920-cmu-misc"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MISC_NOC>; + clock-names = "oscclk", + "noc"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -247,6 +258,19 @@ status = "disabled"; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "samsung,exynosautov920-cmu-peric1"; + reg = <0x10c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC1_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + syscon_peric1: syscon@10c20000 { compatible = "samsung,exynosautov920-peric1-sysreg", "syscon"; @@ -283,12 +307,38 @@ reg = <0x11860000 0x10000>; }; + cmu_hsi0: clock-controller@16000000 { + compatible = "samsung,exynosautov920-cmu-hsi0"; + reg = <0x16000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI0_NOC>; + clock-names = "oscclk", + "noc"; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16040000 0x10000>; interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_hsi1: clock-controller@16400000 { + compatible = "samsung,exynosautov920-cmu-hsi1"; + reg = <0x16400000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI1_NOC>, + <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, + <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; + clock-names = "oscclk", + "noc", + "usbdrd", + "mmc_card"; + }; + pinctrl_hsi1: pinctrl@16450000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16450000 0x10000>; |