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| author |   Guo Ren <guoren@linux.alibaba.com> | 2020-08-18 07:31:17 +0000 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-10-07 08:01:25 +0200 |
| commit | 688aa0e0aaf947e397004236318a705181591828 (patch) | |
| tree | 0bec8e5d92de201d4fac0bba279d62b549baf8e1 | |
| parent | drm/amdgpu: restore proper ref count in amdgpu_display_crtc_set_config (diff) | |
| download | wireguard-linux-688aa0e0aaf947e397004236318a705181591828.tar.xz wireguard-linux-688aa0e0aaf947e397004236318a705181591828.zip | |
clocksource/drivers/timer-gx6605s: Fixup counter reload
[ Upstream commit bc6717d55d07110d8f3c6d31ec2af50c11b07091 ]
When the timer counts to the upper limit, an overflow interrupt is
generated, and the count is reset with the value in the TIME_INI
register. But the software expects to start counting from 0 when
the count overflows, so it forces TIME_INI to 0 to solve the
potential interrupt storm problem.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Tested-by: Xu Kai <xukai@nationalchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/1597735877-71115-1-git-send-email-guoren@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | drivers/clocksource/timer-gx6605s.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clocksource/timer-gx6605s.c b/drivers/clocksource/timer-gx6605s.c index 80d0939d040b..8d386adbe800 100644 --- a/drivers/clocksource/timer-gx6605s.c +++ b/drivers/clocksource/timer-gx6605s.c @@ -28,6 +28,7 @@ static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev) void __iomem *base = timer_of_base(to_timer_of(ce)); writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); + writel_relaxed(0, base + TIMER_INI); ce->event_handler(ce); |