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author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2020-12-25 15:52:53 +0800 |
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committer | Vinod Koul <vkoul@kernel.org> | 2021-01-13 18:22:17 +0530 |
commit | 5ada755de9db0053740e73ea264393a20fc5eded (patch) | |
tree | 4ce86e64350019c9dcf1ea5a891ef9d6b8d33b9b /Documentation/devicetree/bindings/display/mediatek | |
parent | dt-bindings: phy: convert phy-mtk-ufs.txt to YAML schema (diff) | |
download | wireguard-linux-5ada755de9db0053740e73ea264393a20fc5eded.tar.xz wireguard-linux-5ada755de9db0053740e73ea264393a20fc5eded.zip |
dt-bindings: phy: convert HDMI PHY binding to YAML schema
Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20201225075258.33352-6-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/display/mediatek')
-rw-r--r-- | Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt index 6b1c586403e4..b284ca51b913 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt @@ -53,23 +53,7 @@ Required properties: HDMI PHY ======== - -The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel -output and drives the HDMI pads. - -Required properties: -- compatible: "mediatek,<chip>-hdmi-phy" -- the supported chips are mt2701, mt7623 and mt8173 -- reg: Physical base address and length of the module's registers -- clocks: PLL reference clock -- clock-names: must contain "pll_ref" -- clock-output-names: must be "hdmitx_dig_cts" on mt8173 -- #phy-cells: must be <0> -- #clock-cells: must be <0> - -Optional properties: -- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa -- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c +See phy/mediatek,hdmi-phy.yaml Example: |