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| author |   Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2013-06-13 11:23:38 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2013-06-18 16:15:18 +0900 |
| commit | 894db164260c39870ea79e473e1307b4aa5e4257 (patch) | |
| tree | 108e8b9252f79fcdf4e1a58507300f255cedce5f /Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | |
| parent | ARM: shmobile: marzen-reference: add irqpin support in DT (diff) | |
| download | wireguard-linux-894db164260c39870ea79e473e1307b4aa5e4257.tar.xz wireguard-linux-894db164260c39870ea79e473e1307b4aa5e4257.zip | |
irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Most Renesas irqpin controllers have 4-bit sense fields, however, some
have different widths. This patch adds a DT binding to optionally
specify such non-standard values.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file mode 100644 index 000000000000..66fcaf5b09ff --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -0,0 +1,14 @@ +DT bindings for the R-/SH-Mobile irqpin controller + +Required properties: + +- compatible: has to be "renesas,intc-irqpin" +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties +- sense-bitfield-width: width of a single sense bitfield in the SENSE register, + if different from the default 4 bits |