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author | Rob Herring <robh@kernel.org> | 2020-04-17 14:37:05 -0500 |
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committer | Rob Herring <robh@kernel.org> | 2020-04-17 14:37:05 -0500 |
commit | 7e5ff5917593011360dfafd05093d50d21d115fb (patch) | |
tree | 0f7e6c5b28f24534705f6e8fa2084209ead98987 /Documentation/devicetree/bindings/memory-controllers | |
parent | dt-bindings: Clean-up schema indentation formatting (diff) | |
parent | kbuild: check libyaml installation for 'make dt_binding_check' (diff) | |
download | wireguard-linux-7e5ff5917593011360dfafd05093d50d21d115fb.tar.xz wireguard-linux-7e5ff5917593011360dfafd05093d50d21d115fb.zip |
Merge branch 'dt/linus' into dt/next
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml | 41 |
1 files changed, 23 insertions, 18 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 12516bd89cf9..611bda38d187 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -97,30 +97,35 @@ examples: #include <dt-bindings/clock/tegra186-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - memory-controller@2c00000 { - compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; - interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - + bus { #address-cells = <2>; #size-cells = <2>; - ranges = <0x0 0x02c00000 0x02c00000 0x0 0xb0000>; + memory-controller@2c00000 { + compatible = "nvidia,tegra186-mc"; + reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; - /* - * Memory clients have access to all 40 bits that the memory - * controller can address. - */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - external-memory-controller@2c60000 { - compatible = "nvidia,tegra186-emc"; - reg = <0x0 0x02c60000 0x0 0x50000>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA186_CLK_EMC>; - clock-names = "emc"; + external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; - nvidia,bpmp = <&bpmp>; + nvidia,bpmp = <&bpmp>; + }; }; }; |