diff options
| author |   Thierry Reding <treding@nvidia.com> | 2017-06-26 17:33:12 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 12:42:30 +0100 |
| commit | f580fd3f9d78cf0425ab98950796c578d8a82167 (patch) | |
| tree | 5ab1276160226e5cae7291f12c822fcb9bec656a /Documentation/devicetree/bindings/misc | |
| parent | Linux 4.15-rc1 (diff) | |
| download | wireguard-linux-f580fd3f9d78cf0425ab98950796c578d8a82167.tar.xz wireguard-linux-f580fd3f9d78cf0425ab98950796c578d8a82167.zip | |
dt-bindings: misc: Add Tegra186 MISC registers bindings
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
| -rw-r--r-- | Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt new file mode 100644 index 000000000000..892ba4384abc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra186 MISC register block + +The MISC register block found on Tegra186 SoCs contains registers that can be +used to identify a given chip and various strapping options. + +Required properties: +- compatible: Must be: + - Tegra186: "nvidia,tegra186-misc" +- reg: Should contain 2 entries: The first entry gives the physical address + and length of the register region which contains revision and debug + features. The second entry specifies the physical address and length + of the register region indicating the strapping options. |