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author | 2025-02-19 08:52:14 +1300 | |
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committer | 2025-02-21 15:07:15 -0800 | |
commit | 96757457da0ee36b99ced7a978476d521dddd49d (patch) | |
tree | b17b27e5aaca4a56c5721a035c81fc2d3369be1d /Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml | |
parent | dt-bindings: net: Add switch ports and interrupts to RTL9300 (diff) | |
download | wireguard-linux-96757457da0ee36b99ced7a978476d521dddd49d.tar.xz wireguard-linux-96757457da0ee36b99ced7a978476d521dddd49d.zip |
dt-bindings: net: Add Realtek MDIO controller
Add dtschema for the MDIO controller found in the RTL9300 Ethernet
switch. The controller is slightly unusual in that direct MDIO
communication is not possible. We model the MDIO controller with the
MDIO buses as child nodes and the PHYs as children of the buses. The
mapping of switch port number to MDIO bus/addr requires the
ethernet-ports sibling to provide the mapping via the phy-handle
property.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250218195216.1034220-4-chris.packham@alliedtelesis.co.nz
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to '')
-rw-r--r-- | Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml index 5d29647bea2d..80eabc170669 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml @@ -54,6 +54,9 @@ patternProperties: 'i2c@[0-9a-f]+$': $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + 'mdio-controller@[0-9a-f]+$': + $ref: realtek,rtl9301-mdio.yaml# + required: - compatible - reg @@ -129,15 +132,43 @@ examples: }; }; + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; + phy-handle = <&phy1>; }; port@1 { reg = <1>; + phy-handle = <&phy2>; }; }; }; |