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authorBjorn Helgaas <bhelgaas@google.com>2017-09-01 16:35:50 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-09-01 16:35:50 -0500
commit96291d565550c1fd363e488cc17cb3189d2e4cc2 (patch)
tree5edda68ba7ef9568df9a8a843a4e5c03be656ed8 /Documentation/devicetree/bindings/pci/xgene-pci.txt
parentPCI: Remove unused "res" variable from pci_resource_io() (diff)
downloadwireguard-linux-96291d565550c1fd363e488cc17cb3189d2e4cc2.tar.xz
wireguard-linux-96291d565550c1fd363e488cc17cb3189d2e4cc2.zip
PCI: Fix typos and whitespace errors
Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/xgene-pci.txt')
-rw-r--r--Documentation/devicetree/bindings/pci/xgene-pci.txt8
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt
index 1070b068c7c6..6fd2decfa66c 100644
--- a/Documentation/devicetree/bindings/pci/xgene-pci.txt
+++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt
@@ -8,7 +8,7 @@ Required properties:
property.
- reg-names: Must include the following entries:
"csr": controller configuration registers.
- "cfg": pcie configuration space registers.
+ "cfg": PCIe configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
@@ -21,11 +21,11 @@ Required properties:
Optional properties:
- status: Either "ok" or "disabled".
-- dma-coherent: Present if dma operations are coherent
+- dma-coherent: Present if DMA operations are coherent
Example:
-SoC specific DT Entry:
+SoC-specific DT Entry:
pcie0: pcie@1f2b0000 {
status = "disabled";
@@ -51,7 +51,7 @@ SoC specific DT Entry:
};
-Board specific DT Entry:
+Board-specific DT Entry:
&pcie0 {
status = "ok";
};