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authorBjorn Helgaas <bhelgaas@google.com>2022-08-04 11:41:58 -0500
committerBjorn Helgaas <bhelgaas@google.com>2022-08-04 11:41:58 -0500
commit9195e6dd9b49b98e2bdfea94a5737142d4f49c6a (patch)
tree5c6776f499dfff494dd5729563994c87ab6bdff8 /Documentation/devicetree/bindings/pci
parentMerge branch 'pci/ctrl/microchip' (diff)
parentPCI: qcom: Allow ASPM L1 and substates for 2.7.0 (diff)
downloadwireguard-linux-9195e6dd9b49b98e2bdfea94a5737142d4f49c6a.tar.xz
wireguard-linux-9195e6dd9b49b98e2bdfea94a5737142d4f49c6a.zip
Merge branch 'pci/ctrl/qcom'
- Add PHY clock source implementation (Dmitry Baryshkov) - Use new clk_regmap_phy_mux_ops for gcc-sm8450 and gcc-sc7280 PCIe pipe clocks (Dmitry Baryshkov) - Set up rev 2.1.0 PARF_PHY before enabling clocks (Christian Marangi) - Power on PHY before accessing IPQ8074 DBI registers to avoid boot hangs (Robert Marko) - Power on PHY before accessing DBI registers on all variants for consistency (Robert Marko) - Remove unnecessary pipe_clk handling since this is done in PHY drivers (Dmitry Baryshkov) - Drop manual pipe_clk_src handling (Dmitry Baryshkov) - Move GEN3_RELATED DBI definitions to common dwc header (Baruch Siach) - Define slot capabilities using generic PCI_EXP_SLTCAP_* macros (Baruch Siach) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Fix DT description typo (Baruch Siach) - Fix DT "compatibles" typo (Johan Hovold) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) * pci/ctrl/qcom: PCI: qcom: Allow ASPM L1 and substates for 2.7.0 dt-bindings: PCI: qcom: Fix reset conditional dt-bindings: PCI: qcom: Fix description typo PCI: qcom: Add IPQ60xx support PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* PCI: dwc: Move GEN3_RELATED DBI definitions to common header PCI: qcom: Drop manual pipe_clk_src handling PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Power on PHY before DBI register accesses PCI: qcom: Power on PHY before IPQ8074 DBI register accesses PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: regmap: add PHY clock source implementation
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie.yaml4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 6b1b2cff110b..7d29e2a45183 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -11,7 +11,7 @@ maintainers:
- Stanimir Varbanov <svarbanov@mm-sol.com>
description: |
- Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
+ Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
PCIe IP.
properties:
@@ -615,7 +615,7 @@ allOf:
- if:
not:
properties:
- compatibles:
+ compatible:
contains:
enum:
- qcom,pcie-msm8996