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authorRob Herring <robh@kernel.org>2020-05-12 15:45:43 -0500
committerRob Herring <robh@kernel.org>2020-05-14 14:43:27 -0500
commitfba5618451d2b3af5e55f8af5ce9c5d3677ad9c4 (patch)
treeeb7b2e3f31c660bb1a332028319639a80a4e062b /Documentation/devicetree/bindings/spi
parentdt-bindings: ufs: ti: Add missing 'additionalProperties: false' (diff)
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dt-bindings: Fix incorrect 'reg' property sizes
The examples template is a 'simple-bus' with a size of 1 cell for had between 2 and 4 cells which really only errors on I2C or SPI type devices with a single cell. The easiest fix in most cases is to change the 'reg' property to for 1 cell address and size. In some cases with child devices having 2 cells, that doesn't make sense so a bus node is needed. Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml2
-rw-r--r--Documentation/devicetree/bindings/spi/spi-sifive.yaml2
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
index c8f0985a8738..e84edcf8b332 100644
--- a/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml
@@ -145,7 +145,7 @@ examples:
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
- reg = <0 0xe6e20000 0 0x0064>;
+ reg = <0xe6e20000 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
index fb583e57c1f2..4932205d1cba 100644
--- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml
@@ -70,7 +70,7 @@ examples:
- |
spi: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
interrupt-parent = <&plic>;
interrupts = <51>;
clocks = <&tlclk>;