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| author |   James Morse <james.morse@arm.com> | 2019-06-07 16:14:07 +0100 |
|---|---|---|
| committer |   Jonathan Corbet <corbet@lwn.net> | 2019-06-20 14:16:04 -0600 |
| commit | 7c7a49958286fee9a2b18baffc9c626304a00843 (patch) | |
| tree | edc15d267e28e7d6e94195ba3a8a4a717ed29e55 /Documentation/x86 | |
| parent | Documentation: x86: Contiguous cbm isn't all X86 (diff) | |
| download | wireguard-linux-7c7a49958286fee9a2b18baffc9c626304a00843.tar.xz wireguard-linux-7c7a49958286fee9a2b18baffc9c626304a00843.zip | |
Documentation: x86: Remove cdpl2 unspported statement and fix capitalisation
"L2 cache does not support code and data prioritization". This isn't
true, elsewhere the document says it can be enabled with the cdpl2
mount option.
While we're here, these sample strings have lower-case code/data,
which isn't how the kernel exports them.
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/x86')
| -rw-r--r-- | Documentation/x86/resctrl_ui.rst | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/Documentation/x86/resctrl_ui.rst b/Documentation/x86/resctrl_ui.rst index 066f94e53418..638cd987937d 100644 --- a/Documentation/x86/resctrl_ui.rst +++ b/Documentation/x86/resctrl_ui.rst @@ -418,16 +418,22 @@ L3 schemata file details (CDP enabled via mount option to resctrl) When CDP is enabled L3 control is split into two separate resources so you can specify independent masks for code and data like this:: - L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... - L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... + L3DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... + L3CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... L2 schemata file details ------------------------ -L2 cache does not support code and data prioritization, so the -schemata format is always:: +CDP is supported at L2 using the 'cdpl2' mount option. The schemata +format is either:: L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... +or + + L2DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... + L2CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... + + Memory bandwidth Allocation (default mode) ------------------------------------------ |