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| author |   Thomas Gleixner <tglx@linutronix.de> | 2016-07-04 12:26:05 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2016-07-04 12:26:05 +0200 |
| commit | 8658be133baa92c06b6d832a436d437deb2e2a22 (patch) | |
| tree | 8f798f4aae5892533831487e4838a85b95414a0f /arch/arc/mm/cache.c | |
| parent | Merge tag 'irqchip-core-4.8-2' of git://git.infradead.org/users/jcooper/linux into irq/core (diff) | |
| parent | genirq: Add a helper to spread an affinity mask for MSI/MSI-X vectors (diff) | |
| download | wireguard-linux-8658be133baa92c06b6d832a436d437deb2e2a22.tar.xz wireguard-linux-8658be133baa92c06b6d832a436d437deb2e2a22.zip | |
Merge branch 'irq/for-block' into irq/core
Pull the irq affinity managing code which is in a seperate branch for block
developers to pull.
Diffstat (limited to '')
| -rw-r--r-- | arch/arc/mm/cache.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c index 9e5eddbb856f..5a294b2c3cb3 100644 --- a/arch/arc/mm/cache.c +++ b/arch/arc/mm/cache.c @@ -215,7 +215,7 @@ slc_chk: * ------------------ * This ver of MMU supports variable page sizes (1k-16k): although Linux will * only support 8k (default), 16k and 4k. - * However from hardware perspective, smaller page sizes aggrevate aliasing + * However from hardware perspective, smaller page sizes aggravate aliasing * meaning more vaddr bits needed to disambiguate the cache-line-op ; * the existing scheme of piggybacking won't work for certain configurations. * Two new registers IC_PTAG and DC_PTAG inttoduced. @@ -302,7 +302,7 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr, /* * This is technically for MMU v4, using the MMU v3 programming model - * Special work for HS38 aliasing I-cache configuratino with PAE40 + * Special work for HS38 aliasing I-cache configuration with PAE40 * - upper 8 bits of paddr need to be written into PTAG_HI * - (and needs to be written before the lower 32 bits) * Note that PTAG_HI is hoisted outside the line loop @@ -936,7 +936,7 @@ void arc_cache_init(void) ic->ver, CONFIG_ARC_MMU_VER); /* - * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG + * In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 */ if (is_isa_arcv2() && ic->alias) |