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| author |   Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2020-07-10 07:19:37 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2020-07-13 19:48:53 +0800 |
| commit | fa28d8212ede9c533ae87a737571a9d3b3eebb29 (patch) | |
| tree | 72b8f82b0e6c85a4703e88864b738e5025e8f270 /arch/arm/boot/dts/imx51.dtsi | |
| parent | ARM: dts: vf610-zii-scu4-aib: Configure fibre ports to 1000BaseX (diff) | |
| download | wireguard-linux-fa28d8212ede9c533ae87a737571a9d3b3eebb29.tar.xz wireguard-linux-fa28d8212ede9c533ae87a737571a9d3b3eebb29.zip | |
ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files
The imx-pwm driver supports 3 cells and this is the more flexible setting.
So use it by default and overwrite it back to two for the files that
reference the PWMs with just 2 cells to minimize changes.
This allows to drop explicit setting to 3 cells for the boards that already
depend on this. The boards that are now using 2 cells explicitly can be
converted to 3 individually.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx51.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx51.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index db5827d62c3c..985e1be03ad6 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -400,7 +400,7 @@ }; pwm1: pwm@73fb4000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, @@ -410,7 +410,7 @@ }; pwm2: pwm@73fb8000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |