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| author |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2020-01-10 18:20:06 +0100 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2020-01-10 18:25:14 +0100 |
| commit | ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da (patch) | |
| tree | 5262a34909cd711cc5d9dfb29cdce30fd4f579be /arch/arm/boot/dts/sama5d3_uart.dtsi | |
| parent | ARM: dts: at91: nattis 2: remove unnecessary include (diff) | |
| download | wireguard-linux-ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da.tar.xz wireguard-linux-ee0aa926ddb0bd8ba59e33e3803b3b5804e3f5da.zip | |
ARM: dts: at91: sama5d3: fix maximum peripheral clock rates
Currently the maximum rate for peripheral clock is calculated based on a
typical 133MHz MCK. The maximum frequency is defined in the datasheet as a
ratio to MCK. Some sama5d3 platforms are using a 166MHz MCK. Update the
device trees to match the maximum rate based on 166MHz.
Reported-by: Karl Rudbæk Olsen <karl@micro-technic.com>
Fixes: d2e8190b7916 ("ARM: at91/dt: define sama5d3 clocks")
Link: https://lore.kernel.org/r/20200110172007.1253659-1-alexandre.belloni@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sama5d3_uart.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sama5d3_uart.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 4316bdbdc25d..cb62adbd28ed 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -41,13 +41,13 @@ uart0_clk: uart0_clk { #clock-cells = <0>; reg = <16>; - atmel,clk-output-range = <0 66000000>; + atmel,clk-output-range = <0 83000000>; }; uart1_clk: uart1_clk { #clock-cells = <0>; reg = <17>; - atmel,clk-output-range = <0 66000000>; + atmel,clk-output-range = <0 83000000>; }; }; }; |