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| author |   David S. Miller <davem@davemloft.net> | 2012-10-02 23:02:10 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-10-02 23:02:10 -0400 |
| commit | 954f9ac43b87b44152b8c21163cefd466a87145e (patch) | |
| tree | 31c4197f975c66c96976948663e6ce844900b41a /arch/arm/mach-omap2/irq.c | |
| parent | sparc64: Fix return value of Niagara-2 memcpy. (diff) | |
| parent | Merge tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc (diff) | |
| download | wireguard-linux-954f9ac43b87b44152b8c21163cefd466a87145e.tar.xz wireguard-linux-954f9ac43b87b44152b8c21163cefd466a87145e.zip | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
There's a Niagara 2 memcpy fix in this tree and I have
a Kconfig fix from Dave Jones which requires the sparc-next
changes which went upstream yesterday.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm/mach-omap2/irq.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bcd83db41bbc..3926f370448f 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -23,8 +23,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> -#include <mach/hardware.h> - +#include "soc.h" #include "iomap.h" #include "common.h" @@ -49,6 +48,8 @@ #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */ #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ +#define INTCPS_NR_MIR_REGS 3 +#define INTCPS_NR_IRQS 96 /* * OMAP2 has a number of different interrupt controllers, each interrupt @@ -107,9 +108,8 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) unsigned long tmp; tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; - printk(KERN_INFO "IRQ: Found an INTC at 0x%p " - "(revision %ld.%ld) with %d interrupts\n", - bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); + pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", + bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); tmp |= 1 << 1; /* soft reset */ |