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| author |   Hector Martin <marcan@marcan.st> | 2022-02-15 21:34:10 +0900 |
|---|---|---|
| committer | Hector Martin <marcan@marcan.st> | 2022-12-04 13:31:59 +0900 |
| commit | d32c1530c7230b756ca9a6b6cf92ce6e60788594 (patch) | |
| tree | c1014f1372fc564e8d29e766e2676862e71c23bf /arch/arm64/boot/dts/apple/t6002.dtsi | |
| parent | arm64: dts: apple: Add CPU topology & cpufreq nodes for t8103 (diff) | |
| download | wireguard-linux-d32c1530c7230b756ca9a6b6cf92ce6e60788594.tar.xz wireguard-linux-d32c1530c7230b756ca9a6b6cf92ce6e60788594.zip | |
arm64: dts: apple: Add CPU topology & cpufreq nodes for t600x
Add the missing CPU topology/capacity information and the cpufreq nodes,
so we can have CPU frequency scaling and the scheduler has the
information it needs to make the correct decisions.
As with t8103, boost states are commented out pending PSCI/etc support
for deep sleep states.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
Diffstat (limited to 'arch/arm64/boot/dts/apple/t6002.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/apple/t6002.dtsi | 72 |
1 files changed, 71 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 731d61fbb05f..15da2c7eb1fe 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -23,6 +23,47 @@ #size-cells = <2>; cpus { + cpu-map { + cluster3 { + core0 { + cpu = <&cpu_e10>; + }; + core1 { + cpu = <&cpu_e11>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu_p20>; + }; + core1 { + cpu = <&cpu_p21>; + }; + core2 { + cpu = <&cpu_p22>; + }; + core3 { + cpu = <&cpu_p23>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu_p30>; + }; + core1 { + cpu = <&cpu_p31>; + }; + core2 { + cpu = <&cpu_p32>; + }; + core3 { + cpu = <&cpu_p33>; + }; + }; + }; + cpu_e10: cpu@800 { compatible = "apple,icestorm"; device_type = "cpu"; @@ -32,6 +73,9 @@ next-level-cache = <&l2_cache_3>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e_die1>; }; cpu_e11: cpu@801 { @@ -43,6 +87,9 @@ next-level-cache = <&l2_cache_3>; i-cache-size = <0x20000>; d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e_die1>; }; cpu_p20: cpu@10900 { @@ -54,6 +101,9 @@ next-level-cache = <&l2_cache_4>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; }; cpu_p21: cpu@10901 { @@ -65,6 +115,9 @@ next-level-cache = <&l2_cache_4>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; }; cpu_p22: cpu@10902 { @@ -76,6 +129,9 @@ next-level-cache = <&l2_cache_4>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; }; cpu_p23: cpu@10903 { @@ -87,6 +143,9 @@ next-level-cache = <&l2_cache_4>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; }; cpu_p30: cpu@10a00 { @@ -98,6 +157,9 @@ next-level-cache = <&l2_cache_5>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; }; cpu_p31: cpu@10a01 { @@ -109,6 +171,9 @@ next-level-cache = <&l2_cache_5>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; }; cpu_p32: cpu@10a02 { @@ -120,6 +185,9 @@ next-level-cache = <&l2_cache_5>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; }; cpu_p33: cpu@10a03 { @@ -131,6 +199,9 @@ next-level-cache = <&l2_cache_5>; i-cache-size = <0x30000>; d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; }; l2_cache_3: l2-cache-3 { @@ -206,7 +277,6 @@ #undef DIE #undef DIE_NO - &aic { affinities { e-core-pmu-affinity { |