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| author |   Krzysztof Kozlowski <krzk@kernel.org> | 2020-08-28 18:47:37 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2020-09-05 14:22:41 +0800 |
| commit | 0a96ec9bddd1622267e42b75994f21615a5d1f85 (patch) | |
| tree | 8c20dbd6ca77c6faaf16918bbabac707b4eff303 /arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | |
| parent | arm64: dts: imx8mm: Add imx8mm ddr4 evk board support (diff) | |
| download | wireguard-linux-0a96ec9bddd1622267e42b75994f21615a5d1f85.tar.xz wireguard-linux-0a96ec9bddd1622267e42b75994f21615a5d1f85.zip | |
arm64: dts: imx8mm-beacon: Align pin configuration group names with schema
Device tree schema expects pin configuration groups to end with 'grp'
suffix. This fixes dtbs_check warnings like:
pinctrl@30330000: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz', 'usdhc1grp200mhz', 'usdhc1grpgpio',
'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz', 'usdhc3grp200mhz'
do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 5b5af8b381df..d6b9dedd168f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -210,7 +210,7 @@ >; }; - pinctrl_pcal6414: pcal6414-gpio { + pinctrl_pcal6414: pcal6414-gpiogrp { fsl,pins = < MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 >; @@ -240,7 +240,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 @@ -259,7 +259,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -271,7 +271,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |