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| author |   Lucas Stach <l.stach@pengutronix.de> | 2021-12-13 21:40:47 +0100 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2021-12-16 16:08:03 +0800 |
| commit | 842912c42e88748648901e22c238834f7a6ccb26 (patch) | |
| tree | 3037e07788831eb2f7da424f6d522bb20bea4700 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | arm64: dts: nitrogen8-som: correct i2c1 pad-ctrl (diff) | |
| download | wireguard-linux-842912c42e88748648901e22c238834f7a6ccb26.tar.xz wireguard-linux-842912c42e88748648901e22c238834f7a6ccb26.zip | |
arm64: dts: imx8mm: don't assign PLL2 in SoC dtsi
The base i.MX8MM dtsi changes the audio PLL2 rate, which gets in the
way if it should be used for anything else than audio. As this PLL doesn't
seem to be used by any upstream supported board, just remove the rate
configuration to allow boards to set it up as they wish.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c84d76860441..f77f90ed416f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -619,8 +619,7 @@ <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, - <&clk IMX8MM_AUDIO_PLL1>, - <&clk IMX8MM_AUDIO_PLL2>; + <&clk IMX8MM_AUDIO_PLL1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, <&clk IMX8MM_SYS_PLL3_OUT>, @@ -630,8 +629,7 @@ <400000000>, <750000000>, <594000000>, - <393216000>, - <361267200>; + <393216000>; }; src: reset-controller@30390000 { |