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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-09-02 10:11:51 +0200 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2022-09-13 18:59:01 +0200 |
| commit | e775cc1a9b4fb9b7b62edc480642ebd21e3b81e1 (patch) | |
| tree | 11c5df1bac87651bd7ecd8e47a5130a24283a78f /arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | |
| parent | arm64: dts: mediatek: cherry: Enable the System Companion Processor (diff) | |
| download | wireguard-linux-e775cc1a9b4fb9b7b62edc480642ebd21e3b81e1.tar.xz wireguard-linux-e775cc1a9b4fb9b7b62edc480642ebd21e3b81e1.zip | |
arm64: dts: mediatek: cherry: Wire up the ChromeOS Embedded Controller
Wire up the ChromeOS Embedded Controller on SPI0 and its communication
channel via SCP RPMSG along with all of the offered functionality,
including Keyboard, Smart Battery Metrics (SBS), keyboard backlight,
I2C tunnel, regulators and Type-C connector management.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220902081156.38526-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e83d58d99757..73f531f84fa2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -426,6 +426,14 @@ "AP_SPI_FLASH_MOSI", "AP_SPI_FLASH_MISO"; + cros_ec_int: cros-ec-irq-default-pins { + pins-ec-ap-int-odl { + pinmux = <PINMUX_GPIO4__FUNC_GPIO4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + input-enable; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = <PINMUX_GPIO8__FUNC_SDA0>, @@ -670,6 +678,11 @@ memory-region = <&scp_mem>; pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; + + cros-ec-rpmsg { + compatible = "google,cros-ec-rpmsg"; + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; }; &spi0 { @@ -678,6 +691,67 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; mediatek,pad-select = <0>; + + cros_ec: ec@0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + spi-max-frequency = <3000000>; + + keyboard-backlight { + compatible = "google,cros-kbd-led-backlight"; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mt_pmic_vmc_ldo_reg: regulator@0 { + compatible = "google,cros-ec-regulator"; + reg = <0>; + regulator-name = "mt_pmic_vmc_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + }; + + mt_pmic_vmch_ldo_reg: regulator@1 { + compatible = "google,cros-ec-regulator"; + reg = <1>; + regulator-name = "mt_pmic_vmch_ldo"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; }; &u3phy0 { @@ -729,3 +803,6 @@ vusb33-supply = <&mt6359_vusb_ldo_reg>; vbus-supply = <&usb_vbus>; }; + +#include <arm/cros-ec-keyboard.dtsi> +#include <arm/cros-ec-sbs.dtsi> |