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| author |   Biju Das <biju.das@bp.renesas.com> | 2019-09-23 15:57:25 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2019-10-10 16:22:07 +0200 |
| commit | ce21f29032ae49a0bb2a260ab5ebf4c516c9f6e9 (patch) | |
| tree | bcf3de345f518fd851e1ad369aed2757b0f8d186 /arch/arm64/boot/dts/renesas/r8a774b1.dtsi | |
| parent | arm64: dts: renesas: Add HiHope RZ/G2N sub board support (diff) | |
| download | wireguard-linux-ce21f29032ae49a0bb2a260ab5ebf4c516c9f6e9.tar.xz wireguard-linux-ce21f29032ae49a0bb2a260ab5ebf4c516c9f6e9.zip | |
arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices
This patch adds OPPs table for CA57{0,1} cpu devices.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569250648-33857-2-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a774b1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f42f6463453f..398bf3861254 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -45,6 +45,28 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -59,6 +81,7 @@ #cooling-cells = <2>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -69,6 +92,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; L2_CA57: cache-controller-0 { |