diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-07-30 13:24:34 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-08-23 15:43:27 +0200 |
| commit | ab39547f739236e7f16b8b0a51fdca95cc9cadd3 (patch) | |
| tree | dfc8b3a78f2e5a10af8bcdc6be3d9d80f964ff59 /arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | |
| parent | arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes (diff) | |
| download | wireguard-linux-ab39547f739236e7f16b8b0a51fdca95cc9cadd3.tar.xz wireguard-linux-ab39547f739236e7f16b8b0a51fdca95cc9cadd3.zip | |
arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes
The RZ/G2UL SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB
for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU.
Despite the RZ/G2UL SoC being single-core, it has two instances of GICR.
Fixes: cf40c9689e510 ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 18ef297db933..20fb5e41c598 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -210,8 +210,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; }; |