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| author |   Heiko Stuebner <heiko@sntech.de> | 2019-09-17 10:26:50 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-10-03 23:23:42 +0200 |
| commit | cdfebb27892a66580d770f6c57f3deb5024b4d08 (patch) | |
| tree | 46d45395234ee3be880f79a206111d10f59c4812 /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | arm64: dts: rockchip: remove px30 emmc_pwren pinctrl (diff) | |
| download | wireguard-linux-cdfebb27892a66580d770f6c57f3deb5024b4d08.tar.xz wireguard-linux-cdfebb27892a66580d770f6c57f3deb5024b4d08.zip | |
arm64: dts: rockchip: add default px30 emmc pinctrl
emmc chips are normally hooked up in standard ways using the full 8bit
bus connection, so there should be no need for all future boards to define
this on their own. So add default pin setups for 8bit busses and special
boards really only needing 4 or 1 bit connections can override.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20190917082659.25549-4-heiko@sntech.de
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index a178d6e2c279..f2bbdfa0e4aa 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -794,6 +794,8 @@ clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; fifo-depth = <0x100>; max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; power-domains = <&power PX30_PD_MMC_NAND>; status = "disabled"; }; |