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authorHeiko Stuebner <heiko.stuebner@theobroma-systems.com>2021-07-22 09:39:55 +0200
committerHeiko Stuebner <heiko@sntech.de>2021-09-15 17:50:22 +0200
commite2425dcc70115afc1eeb09d78f56239872824022 (patch)
treea6905ef5f62eb40b36252a9cbe2a27b27247c569 /arch/arm64/boot/dts/rockchip/px30.dtsi
parentarm64: dts: rockchip: add SPDIF node for ROCK Pi 4 (diff)
downloadwireguard-linux-e2425dcc70115afc1eeb09d78f56239872824022.tar.xz
wireguard-linux-e2425dcc70115afc1eeb09d78f56239872824022.zip
arm64: dts: rockchip: add csi-dphy to px30
Add the CSI dphy node to the core px30 devicetree for later use with the rkisp. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210722073955.1192168-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/px30.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 248ebb61aa79..6e53a4cc75e6 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -864,6 +864,19 @@
status = "disabled";
};
+ csi_dphy: phy@ff2f0000 {
+ compatible = "rockchip,px30-csi-dphy";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ clocks = <&cru PCLK_MIPICSIPHY>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power PX30_PD_VI>;
+ resets = <&cru SRST_MIPICSIPHY_P>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
usb20_otg: usb@ff300000 {
compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
"snps,dwc2";