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| author |   Tomi Valkeinen <tomi.valkeinen@ti.com> | 2022-04-29 16:56:38 +0530 |
|---|---|---|
| committer |   Vignesh Raghavendra <vigneshr@ti.com> | 2022-05-05 22:45:16 +0530 |
| commit | 92c996f4ceabd5780bb7678138267db0a1e1a00e (patch) | |
| tree | 9d13adfb79f4dcc09d52d4a1e5d6ba0a77d5e80b /arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | |
| parent | arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_main (diff) | |
| download | wireguard-linux-92c996f4ceabd5780bb7678138267db0a1e1a00e.tar.xz wireguard-linux-92c996f4ceabd5780bb7678138267db0a1e1a00e.zip | |
arm64: dts: ti: k3-j721e-*: add DP & DP PHY
Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
Also add the required phy link nodes in the board dts files.
A slight irregularity in the bindings is the DPTX PHY register block,
which is in the MHDP IP, but is needed and mapped by the PHY.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Aradhya Bhatia <a-bhatia1@ti.com>
Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index f5ca8e26ed99..2f119e94e783 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -793,6 +793,22 @@ }; }; +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; +}; + &pcie0_rc { reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; |