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| author |   Nishanth Menon <nm@ti.com> | 2020-09-30 07:32:50 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2020-09-30 07:32:50 -0500 |
| commit | ffb0024ecd3d3e20b8eb1d0d54ceeb7f43453118 (patch) | |
| tree | f55c39fc81db04fa8b5f12e11de9ccdc8dbb5020 /arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | |
| parent | arm64: dts: ti: k3-j721e-common-proc-board: align GPIO hog names with dtschema (diff) | |
| parent | arm64: dts: ti: k3-j721e: Rename mux header and update macro names (diff) | |
| download | wireguard-linux-ffb0024ecd3d3e20b8eb1d0d54ceeb7f43453118.tar.xz wireguard-linux-ffb0024ecd3d3e20b8eb1d0d54ceeb7f43453118.zip | |
Merge tag 'ti-k3-dt-fixes-for-v5.9' into ti-k3-dts-next
Merge fix up for TI serdes mux definition introduced in 5.9 as
dependency for 5.10 series on J7200 USB.
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 917421ed3f79..52e121155563 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -311,11 +311,12 @@ }; &serdes_ln_ctrl { - idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, - <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, - <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, - <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>, - <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; + idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, + <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; }; &serdes_wiz3 { |