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| author |   Shanker Donthineni <shankerd@codeaurora.org> | 2018-03-05 11:06:43 -0600 |
|---|---|---|
| committer |   Marc Zyngier <marc.zyngier@arm.com> | 2018-03-19 18:35:38 +0000 |
| commit | f9f5dc19509bbef6f5e675346f1a7d7b846bdb12 (patch) | |
| tree | 76ddea08ea7d770e850adc95203e5dc165d362a1 /arch/arm64/kvm/hyp/switch.c | |
| parent | KVM: arm: Reserve bit in KVM_REG_ARM encoding for secure/nonsecure (diff) | |
| download | wireguard-linux-f9f5dc19509bbef6f5e675346f1a7d7b846bdb12.tar.xz wireguard-linux-f9f5dc19509bbef6f5e675346f1a7d7b846bdb12.zip | |
arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC
V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses
the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead
of Silicon provider service ID 0xC2001700.
Cc: <stable@vger.kernel.org> # 4.14+
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/kvm/hyp/switch.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 07b572173265..d9645236e474 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -472,16 +472,6 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu) /* And we're baaack! */ } while (fixup_guest_exit(vcpu, &exit_code)); - if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) { - u32 midr = read_cpuid_id(); - - /* Apply BTAC predictors mitigation to all Falkor chips */ - if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) || - ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) { - __qcom_hyp_sanitize_btac_predictors(); - } - } - fp_enabled = __fpsimd_enabled_nvhe(); __sysreg_save_state_nvhe(guest_ctxt); |