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| author |   Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:55:21 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:55:21 -0700 |
| commit | bbb20089a3275a19e475dbc21320c3742e3ca423 (patch) | |
| tree | 216fdc1cbef450ca688135c5b8969169482d9a48 /arch/blackfin/mach-common/clocks-init.c | |
| parent | Merge branch 'iop-raid6' into async-tx-next (diff) | |
| parent | dmaengine: Move all map_sg/unmap_sg for slave channel to its client (diff) | |
| download | wireguard-linux-bbb20089a3275a19e475dbc21320c3742e3ca423.tar.xz wireguard-linux-bbb20089a3275a19e475dbc21320c3742e3ca423.zip | |
Merge branch 'dmaengine' into async-tx-next
Conflicts:
crypto/async_tx/async_xor.c
drivers/dma/ioat/dma_v2.h
drivers/dma/ioat/pci.c
drivers/md/raid5.c
Diffstat (limited to 'arch/blackfin/mach-common/clocks-init.c')
| -rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 35393651359b..ef6870e9eea6 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c @@ -72,6 +72,7 @@ void init_clocks(void) #endif bfin_write_PLL_LOCKCNT(0x300); do_sync(); + /* We always write PLL_CTL thus avoiding Anomaly 05000242 */ bfin_write16(PLL_CTL, PLL_CTL_VAL); __asm__ __volatile__("IDLE;"); bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); |