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| author |   Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:53:04 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 17:53:04 -0700 |
| commit | 162b96e63e518aa6ff029ce23de12d7f027483bf (patch) | |
| tree | 532191d0cef7cf975b70a07b1c69a293d6f552f7 /arch/m32r/kernel/init_task.c | |
| parent | dmaengine: kill tx_list (diff) | |
| download | wireguard-linux-162b96e63e518aa6ff029ce23de12d7f027483bf.tar.xz wireguard-linux-162b96e63e518aa6ff029ce23de12d7f027483bf.zip | |
ioat2,3: cacheline align software descriptor allocations
All the necessary fields for handling an ioat2,3 ring entry can fit into
one cacheline. Move ->len prior to ->txd in struct ioat_ring_ent, and
move allocation of these entries to a hw-cache-aligned kmem cache to
reduce the number of cachelines dirtied for descriptor management.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/m32r/kernel/init_task.c')
0 files changed, 0 insertions, 0 deletions