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| author |   Christoph Hellwig <hch@lst.de> | 2020-04-16 17:00:08 +0200 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-04-19 16:10:24 +0200 |
| commit | 5c9ff5709dcf82bfd9a6d0d99a13b15ca522f510 (patch) | |
| tree | 12155ca4ce7c23c68cb4ad46cf42d4bc0ba7cdb3 /arch/mips/include/asm/io.h | |
| parent | MIPS: cleanup fixup_bigphys_addr handling (diff) | |
| download | wireguard-linux-5c9ff5709dcf82bfd9a6d0d99a13b15ca522f510.tar.xz wireguard-linux-5c9ff5709dcf82bfd9a6d0d99a13b15ca522f510.zip | |
MIPS: merge __ioremap_mode into ioremap_prot
There is no reason to have two ioremap with flags interfaces. Merge
the historic mips __ioremap_mode into ioremap_prot which is a generic
kernel interface.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/io.h')
| -rw-r--r-- | arch/mips/include/asm/io.h | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 7be323ed2bfd..60513250f8f8 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -156,9 +156,17 @@ static inline void *isa_bus_to_virt(unsigned long address) extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); extern void __iounmap(const volatile void __iomem *addr); -static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size, - unsigned long flags) +/* + * ioremap_prot - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + + * ioremap_prot gives the caller control over cache coherency attributes (CCA) + */ +static inline void __iomem *ioremap_prot(phys_addr_t offset, + unsigned long size, unsigned long prot_val) { + unsigned long flags = prot_val & _CACHE_MASK; void __iomem *addr = plat_ioremap(offset, size, flags); if (addr) @@ -203,18 +211,6 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si } /* - * ioremap_prot - map bus memory into CPU space - * @offset: bus address of the memory - * @size: size of the resource to map - - * ioremap_prot gives the caller control over cache coherency attributes (CCA) - */ -static inline void __iomem *ioremap_prot(phys_addr_t offset, - unsigned long size, unsigned long prot_val) { - return __ioremap_mode(offset, size, prot_val & _CACHE_MASK); -} - -/* * ioremap - map bus memory into CPU space * @offset: bus address of the memory * @size: size of the resource to map @@ -226,7 +222,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * address. */ #define ioremap(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED) + ioremap_prot((offset), (size), _CACHE_UNCACHED) #define ioremap_uc ioremap /* @@ -245,7 +241,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * memory-like regions on I/O busses. */ #define ioremap_cache(offset, size) \ - __ioremap_mode((offset), (size), _page_cachable_default) + ioremap_prot((offset), (size), _page_cachable_default) /* * ioremap_wc - map bus memory into CPU space @@ -266,7 +262,7 @@ static inline void __iomem *ioremap_prot(phys_addr_t offset, * _CACHE_UNCACHED option (see cpu_probe() method). */ #define ioremap_wc(offset, size) \ - __ioremap_mode((offset), (size), boot_cpu_data.writecombine) + ioremap_prot((offset), (size), boot_cpu_data.writecombine) static inline void iounmap(const volatile void __iomem *addr) { |