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| author |   Manuel Lauss <manuel.lauss@gmail.com> | 2015-02-18 11:01:56 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-02-20 13:01:42 +0100 |
| commit | 69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c (patch) | |
| tree | e568482e3fd178211e3caa00f9cb4d64ae31a804 /arch/mips/include/asm/processor.h | |
| parent | MIPS: Alchemy: remove declaration for set_cpuspec (diff) | |
| download | wireguard-linux-69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c.tar.xz wireguard-linux-69e4e63ec816a7e22cc3aa14bc7ef4ac734d370c.zip | |
MIPS: Alchemy: Fix cpu clock calculation
The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed. However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.
This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Reported-by: John Crispin <blogic@openwrt.org>
Tested-by: Bruno Randolf <br1@einfach.org>
Cc: stable@vger.kernel.org [v3.17+]
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/processor.h')
0 files changed, 0 insertions, 0 deletions