diff options
| author |   Daniel Yeisley <dan.yeisley@unisys.com> | 2006-05-30 22:47:57 +0200 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@g5.osdl.org> | 2006-05-30 20:31:06 -0700 |
| commit | 0d01532451710110a93891ae152d1dd1ee006ccf (patch) | |
| tree | 565b85776957df727847ffd752018022e83c63f9 /arch/mips/kernel/proc.c | |
| parent | [PATCH] x86_64: fix last_tsc calculation of PM timer (diff) | |
| download | wireguard-linux-0d01532451710110a93891ae152d1dd1ee006ccf.tar.xz wireguard-linux-0d01532451710110a93891ae152d1dd1ee006ccf.zip | |
[PATCH] x86_64: Handle empty node zero
From: Daniel Yeisley <dan.yeisley@unisys.com>
It is possible to boot a Unisys ES7000 with CPUs from multiple cells, and not
also include the memory from those cells. This can create a scenario where
node 0 has cpus, but no associated memory. The system will boot fine in a
configuration where node 0 has memory, but nodes 2 and 3 do not.
[AK: I rechecked the code and generic code seems to indeed handle that already.
Dan's original patch had a change for mm/slab.c that seems to be already in now.]
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips/kernel/proc.c')
0 files changed, 0 insertions, 0 deletions