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| author |   Dan Williams <dan.j.williams@intel.com> | 2010-05-17 16:30:58 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2010-05-17 16:30:58 -0700 |
| commit | 0b28330e39bbe0ffee4c56b09fc415fcec595ea3 (patch) | |
| tree | fcf504879883763557e696eff81427b1ab78f76b /arch/mips/kernel/traps.c | |
| parent | DMAENGINE: extend the control command to include an arg (diff) | |
| parent | async_tx: trim dma_async_tx_descriptor in 'no channel switch' case (diff) | |
| download | wireguard-linux-0b28330e39bbe0ffee4c56b09fc415fcec595ea3.tar.xz wireguard-linux-0b28330e39bbe0ffee4c56b09fc415fcec595ea3.zip | |
Merge branch 'ioat' into dmaengine
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 4e00f9bc23ee..1a4dd657ccb9 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1599,7 +1599,7 @@ void __init trap_init(void) ebase = (unsigned long) __alloc_bootmem(size, 1 << fls(size), 0); } else { - ebase = CAC_BASE; + ebase = CKSEG0; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); } |