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| author | 2012-08-01 20:40:02 +1000 | |
|---|---|---|
| committer | 2012-08-01 20:40:02 +1000 | |
| commit | bb181e2e48f8c85db08c9cb015cbba9618dbf05c (patch) | |
| tree | 191bc24dd97bcb174535cc217af082f16da3b43d /arch/mips/mm/c-r4k.c | |
| parent | md/RAID1: Add missing case for attempting to repair known bad blocks. (diff) | |
| parent | dm raid: move sectors_per_dev calculation (diff) | |
| download | wireguard-linux-bb181e2e48f8c85db08c9cb015cbba9618dbf05c.tar.xz wireguard-linux-bb181e2e48f8c85db08c9cb015cbba9618dbf05c.zip | |
Merge commit 'c039c332f23e794deb6d6f37b9f07ff3b27fb2cf' into md
Pull in pre-requisites for adding raid10 support to dm-raid.
Diffstat (limited to '')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5109be96d98d..f092c265dc63 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) c->icache.linesz = 2 << lsize; else c->icache.linesz = lsize; - c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); c->icache.ways = 1 + ((config1 >> 16) & 7); icache_size = c->icache.sets * @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) c->dcache.linesz = 2 << lsize; else c->dcache.linesz= lsize; - c->dcache.sets = 64 << ((config1 >> 13) & 7); + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); c->dcache.ways = 1 + ((config1 >> 7) & 7); dcache_size = c->dcache.sets * @@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void) case CPU_R14000: break; + case CPU_M14KC: case CPU_24K: case CPU_34K: case CPU_74K: |
