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authorLinus Walleij <linus.walleij@linaro.org>2019-09-05 11:40:54 +0200
committerLinus Walleij <linus.walleij@linaro.org>2019-09-05 11:40:54 +0200
commit151a41014bff92f353263cadc051435dc9c3258e (patch)
treeaa082a0745edd5b7051668f455dfc0ee1e4a9de0 /arch/powerpc/include/asm/cache.h
parentgpio: Fix up merge collision in include file (diff)
parentLinux 5.3-rc7 (diff)
downloadwireguard-linux-151a41014bff92f353263cadc051435dc9c3258e.tar.xz
wireguard-linux-151a41014bff92f353263cadc051435dc9c3258e.zip
Merge tag 'v5.3-rc7' into devel
Linux 5.3-rc7
Diffstat (limited to '')
-rw-r--r--arch/powerpc/include/asm/cache.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index b3388d95f451..45e3137ccd71 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -107,22 +107,22 @@ extern void _set_L3CR(unsigned long);
static inline void dcbz(void *addr)
{
- __asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory");
+ __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbi(void *addr)
{
- __asm__ __volatile__ ("dcbi %y0" : : "Z"(*(u8 *)addr) : "memory");
+ __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbf(void *addr)
{
- __asm__ __volatile__ ("dcbf %y0" : : "Z"(*(u8 *)addr) : "memory");
+ __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
}
static inline void dcbst(void *addr)
{
- __asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory");
+ __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
}
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */