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| author |   Andrea Parri <parri.andrea@gmail.com> | 2019-10-03 17:52:00 +0200 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2019-11-12 11:44:21 +0100 |
| commit | dce7cd62754b5d4a6e401b8b0769ec94cf971041 (patch) | |
| tree | d3ffbd44694b1f6cd044ae85e07c45d70caedca0 /arch/x86/include/asm/hyperv-tlfs.h | |
| parent | x86/hyperv: Micro-optimize send_ipi_one() (diff) | |
| download | wireguard-linux-dce7cd62754b5d4a6e401b8b0769ec94cf971041.tar.xz wireguard-linux-dce7cd62754b5d4a6e401b8b0769ec94cf971041.zip | |
x86/hyperv: Allow guests to enable InvariantTSC
If the hardware supports TSC scaling, Hyper-V will set bit 15 of the
HV_PARTITION_PRIVILEGE_MASK in guest VMs with a compatible Hyper-V
configuration version. Bit 15 corresponds to the
AccessTscInvariantControls privilege. If this privilege bit is set,
guests can access the HvSyntheticInvariantTscControl MSR: guests can
set bit 0 of this synthetic MSR to enable the InvariantTSC feature.
After setting the synthetic MSR, CPUID will enumerate support for
InvariantTSC.
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Link: https://lkml.kernel.org/r/20191003155200.22022-1-parri.andrea@gmail.com
Diffstat (limited to 'arch/x86/include/asm/hyperv-tlfs.h')
| -rw-r--r-- | arch/x86/include/asm/hyperv-tlfs.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h index 7a2705694f5b..887b1d6a15ab 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -86,6 +86,8 @@ #define HV_X64_ACCESS_FREQUENCY_MSRS BIT(11) /* AccessReenlightenmentControls privilege */ #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) +/* AccessTscInvariantControls privilege */ +#define HV_X64_ACCESS_TSC_INVARIANT BIT(15) /* * Feature identification: indicates which flags were specified at partition @@ -270,6 +272,9 @@ #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 +/* TSC invariant control */ +#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 + /* * Declare the MSR used to setup pages used to communicate with the hypervisor. */ |