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| author | 2012-10-19 14:15:16 -0700 | |
|---|---|---|
| committer | 2012-10-19 14:15:16 -0700 | |
| commit | 3b641bf453497d76ea28c5fc1c666f424ead6dcf (patch) | |
| tree | 84dcc02681b3327afcec98481819935606ec5da3 /arch/x86/kernel/cpu/intel_cacheinfo.c | |
| parent | Merge branch 'akpm' (Fixes from Andrew) (diff) | |
| parent | Merge commit '5bc66170dc486556a1e36fd384463536573f4b82' into x86/urgent (diff) | |
| download | wireguard-linux-3b641bf453497d76ea28c5fc1c666f424ead6dcf.tar.xz wireguard-linux-3b641bf453497d76ea28c5fc1c666f424ead6dcf.zip | |
Merge branch 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull miscellaneous x86 fixes from Peter Anvin:
"The biggest ones are fixing suspend/resume breakage on 32 bits, and an
interrim fix for mapping over holes that allows AMD kit with more than
1 TB.
A final solution for the latter is in the works, but involves some
fairly invasive changes that will probably mean it will only be
appropriate for 3.8."
* 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86, MCE: Remove bios_cmci_threshold sysfs attribute
x86, amd, mce: Avoid NULL pointer reference on CPU northbridge lookup
x86: Exclude E820_RESERVED regions and memory holes above 4 GB from direct mapping.
x86/cache_info: Use ARRAY_SIZE() in amd_l3_attrs()
x86/reboot: Remove quirk entry for SBC FITPC
x86, suspend: Correct the restore of CR4, EFER; skip computing EFLAGS.ID
Diffstat (limited to '')
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 9a7c90d80bc4..93c5451bdd52 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -991,7 +991,7 @@ static struct attribute ** __cpuinit amd_l3_attrs(void) if (attrs) return attrs; - n = sizeof (default_attrs) / sizeof (struct attribute *); + n = ARRAY_SIZE(default_attrs); if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) n += 2; |
